1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to a system resource arbitration mechanism in a host bridge.
2. Background
Prior computer systems commonly include a central processing unit (CPU) that communicates with various computer system elements via a host bus. Prior computer systems may also include a peripheral bus that enables communication among a variety of peripheral components. Such a computer system typically includes a host bridge that enables communication between the host bus and the peripheral bus. Such a host bridge typically enables the CPU to access bus agents coupled to the peripheral bus and may enable the bus agents coupled to the peripheral bus to access system resources such as a main memory for the computer system.
Such a computer system typically implements an arbitration mechanism that coordinates accesses to system resources from the host bus and the peripheral bus. For example, such an arbitration mechanism is required to coordinate between main memory accesses by the CPU and main memory accesses by the various bus agents coupled to the peripheral bus. In addition, such an arbitration mechanism typically coordinates between accesses that originate with the CPU and that are targeted for a bus agent on the peripheral bus and accesses that originate on the peripheral bus that are targeted either for a system resource or another bus agent coupled to the peripheral bus.
One type of prior computer system implements a relatively simple arbitration mechanism that employs a set of hold/hold acknowledge bus control signals coupled to the CPU. Such a simple arbitration mechanism asserts the hold signal to the CPU whenever access to system resources is required by one of the bus agents coupled to the peripheral bus. The CPU usually responds to the hold signal from the arbitration mechanism by returning the hold acknowledge signal after completing activity underway on the host bus and any required data coherency transactions.
Such a hold/hold acknowledge implementation provides a relatively low cost arbitration mechanism for a computer system. Unfortunately, such simple hold/hold acknowledge arbitration mechanisms severely limit the performance of the computer system. For example, such arbitration mechanisms usually do not allow concurrent bus transactions over the host bus and the peripheral bus. In addition, such arbitration mechanisms usually do not allow communication between bus agents coupled to the peripheral bus while the CPU is accessing a system resource such as the main memory. Moreover, such a hold/hold acknowledge arbitration mechanism typically requires a long latency between the assertion of the hold signal by the arbitration mechanism and the hold acknowledge response by the CPU. Such long latencies decrease the overall bandwidth available for data transfer in such a system.
Other prior computer systems may implement relatively complex arbitration mechanism. For example, one such computer system employs an arbitration hold/back-off signaling protocol to the CPU on the host bus that allows full concurrent operation between the host bus and the peripheral bus. Such an arbitration hold/back-off signaling protocol typically decreases the latency required for the arbitration mechanism to gain control over the host bus. Unfortunately such an arbitration mechanism usually requires a relatively complex set of arbiter logic in order to ensure proper data flow and data coherency in the system. Such complex arbiter logic typically increases the overall cost of such a computer system.
One object of the present invention is to provide a host bridge with an arbiter that enables a CPU to access main memory while the host bridge completes data transfer posted by the CPU for transfer over the peripheral bus.
Another object of the present invention is to enable a CPU to main memory access to complete in parallel with the start of a main memory access that originates on the peripheral bus.
Another object of the present invention is to enable concurrency between CPU to main memory accesses and communication transactions on the peripheral bus between peripheral bus agent peers.
These and other objects are provided by a computer system that includes a system resource and a host bridge that enables access to the system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. The host bridge provides an arbiter that implements a separate set of priority classes to the CPU and to the bus agents on the peripheral bus for coordinating access to the system resource. For one embodiment, the priority classes for the CPU include a CPU high state and a CPU low state. The arbiter grants priority to the CPU while in the CPU high state and grants access to the separately prioritized bus agents on the peripheral bus while in the CPU low state. The host bridge includes a programmable latency timer that determines an amount of time that the CPU stays in the CPU high state and a programmable watchdog timer that indicates an inactivity time for the CPU for removing the CPU to the CPU low state.
Other features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below.